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Espressif Systems /ESP32-S2 /GPIO /PIN5

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Interpret as PIN5

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SYNC2_BYPASS 0 (PAD_DRIVER)PAD_DRIVER 0SYNC1_BYPASS 0INT_TYPE 0 (WAKEUP_ENABLE)WAKEUP_ENABLE 0CONFIG 0INT_ENA

Description

Configuration for GPIO pin 5

Fields

SYNC2_BYPASS

For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.
PAD_DRIVER

Pad driver selection. 0: normal output; 1: open drain output…
SYNC1_BYPASS

For the first stage synchronization, GPIO input data can be synchro- nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.
INT_TYPE

Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W)
WAKEUP_ENABLE

GPIO wake-up enable bit, only wakes up the CPU from Light-sleep.
CONFIG

Reserved
INT_ENA

Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable interrupt enabled.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data